This invention relates to integrated circuits (IC) comprising a push-pull output driver stage and, more particularly, to a circuit for inhibiting the alternating current (AC) Miller capacitance effect to thereby increase the switching speed and to reduce and/or eliminate transient spikes.
Many bipolar integrated digital logic and interface circuits include a push-pull output driver stage formed by an upper and a lower transistor amplifier connected in cascade between power supply leads. The output of the driver stage is interconnected between the upper and lower transistor amplifiers to a load as is known. For example, U.S. Pat. No. 4,132,906 discloses such a circuit. In order to provide large amounts of output drive current the two transistor amplifiers are typically fabricated with large geometries which give rise to the well known Miller capacitance effect. i.e., a parasitic capacitance is formed between the collector and the base of the transistors and, in particular, between the collector and base of the lower transistor amplifier.
As fully explained in the above referenced '906 patent, a problem arises in such prior art output driver stages during the rapid low-to-high transition at the output of the circuit which, because of the Miller capacitor, may cause undesired transients to occur while reducing the switching speed of the circuit. The subject 906 patent discloses a circuit for improving the rise time while reducing transients in such driver stages.
A very similar problem occurs in output driver stages of logic circuits incorporating push-pull amplifiers which are operated in a three state, power off and normal modes. Three state gates of the type described herein are well known. Although, the circuit described in the '906 patent works quite well for logic circuits of the type described therein, no protection is provided to eliminate or inhibit transients that may arise when a three state gate is operated in an off or three state mode of operation.
For instance, if several three state gates have their outputs tied to a common shared bus, the gate that is in its three state mode of operation could severely load the driving gate if the Miller capacitor effect should cause the lower transistor amplifier of the gate in the three state mode to be rendered conductive as the driving three state gate rapidly transitions from a low-to-high output state.
Additionally, in a shared, three state bus system, where several three state gates drive a single shared bus, a powered down gate can cause loading of the bus when a powered up gate produces a rapid low-to-high transition to occur on the shared bus line.
Still further, in quite the same manner as described in the above referenced patent, during normal operation of a three state gate, when the upper transistor amplifier is turned on, a voltage transient or spike could be produced through the power supply. Thus, if the output rises rapidly in response to the upper transistor amplifier being turned on the Miller parasitic capacitor formed between the collector and base of the lower transistor amplifier could produce base drive to this amplifier that would otherwise allow it to turn on. Absent a transient inhibiting circuit, the upper transistor amplifier would then be severely loaded. In addition, the wasted, undesirable current transients through the lower transistor amplifier can result in significant die heating at high operating frequencies.
Thus, there exists a need to overcome the above undesired problems that may arise in a utilization of integrated three state logic circuits as well as other integrated interface circuits which include push-pull output driver stages incorporated therein.